Design of variable loop gains of dual-loop DPLL

نویسندگان

  • Byungjin Chun
  • Yong Hoon Lee
  • Beomsup Kim
چکیده

An approach to the derivation of variable loop gain sequences of dual-loop digital phase-locked loop (DPLL) [1] is developed based on some modifications of the Kalman filtering formulation. It is shown that optimal loop gain sequences which are independent of measurement noise statistics can be obtained under a deterministic source model. Computer simulation results demonstrate that the adaptive dual-loop DPLL designed by using the proposed method is more robust to noise variations than the adaptive DPLL in [2].

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Design and Implementation of Digital Demodulator for Frequency Modulated CW Radar (RESEARCH NOTE)

Radar Signal Processing has been an interesting area of research for realization of programmable digital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithms have been an integral design methodology for implementation of high speed application specific real-time systems especially for high resolution radar. CORDIC algorithm, in recent times, is turned out to...

متن کامل

Dual-loop Digital PLL Design for Adaptive Clock Recovery

| Since most digital phase-locked loops (DPLLs) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady-state, the DPLL loop bandwidth is preferred to being adjusted accordingly. In this paper, a bandwidth adjusting (adaptive) algorithm is presented, which allow both fast acquisition a...

متن کامل

Neuro-PD Controller of Structural System to Mitigate Earthquake Vibrations

In this paper, stabilization of the structural system against earthquake is presented. Because the conventional PD controller is popular and simple in design, our controller is based on PD controller. The main problem of such a controller is its inability to produce desired response and instability against variations in the properties of the structural system. To obviate this issue, the neu...

متن کامل

Dual Phase Detector Based Delay Locked Loop for High Speed Applications

In this paper a new architecture for delay locked loops will be presented.  One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:
  • IEEE Trans. Communications

دوره 45  شماره 

صفحات  -

تاریخ انتشار 1997